FIELD OF THE INVENTION
This invention relates to the reduction of power consumed by electronic equipment in general. More specifically, this invention relates to the reduction of power consumed by electronic equipment operating in cycles controlled by a time base and in which power consumption can be reduced by inhibiting the time base during periods of load interruption. Such an equipment includes e.g. asynhcronous packet time-division switchers using MOS (Metal Oxyde Semiconductor) type technology.
MOS or CMOS technology is more and more widely used for electronic circuits of all types. Indeed, a circuit using MOS technology has the advantage of very low power consumption. The power consumption of a logic circuit using MOS technology is substantially proportional to the number of logic level transitions carried out in the circuit, and is negligible when the circuit is unused, i.e. in the absence of level transitions. For electronic equipment operating in cycles and using MOS technology, such as e.g. multiplexors, demultiplexors and time-division switchers, a method for reduction of their power consumption comprises inhibiting their cyclic operating during periods of load interruption, i.e. periods during which the equipment has no data signals to process, so as not to foster useless and power consuming level transitions.